It becomes possible to realize a highly functional semiconductor device by consolidating a nonvolatile semiconductor memory cell with a logic semiconductor device on the same silicon (Si) substrate. Such highly functional semiconductor devices are widely used as built-in microcomputers for industrial machines, home appliances, vehicle-installed devices, and others.
A consolidated nonvolatile memory is generally used by storing and retrieving programs required by a microcomputer as needed. As such a nonvolatile memory as to have a cell structure suitable for being consolidated with a logic semiconductor device, there is a memory cell having a split gate structure and comprising a select MOS transistor and a memory MOS transistor.
As methods for retaining electric charge in a memory MOS transistor which is prevailing in consolidated use since the area of peripheral circuitry for the control of memory can be reduced by the adoption of such a structure, there are the floating gate method wherein electric charge is stored in electrically conductive polycrystalline silicon isolated electrically and the MONOS method wherein electric charge is stored in an insulator film, such as an Si nitride film, having the function of storing electric charge.
Either of such electric charge retaining methods is configured so that the region where electric charge is stored is covered by an Si oxide film excellent in electrical isolation. However, the MONOS method has some advantages that: it allows discrete storage since electric charge is stored in an insulator film; it facilitates prediction of reliability since it does not see the radical shortening of charge retention time caused by defects of an Si oxide film; and it has a simple memory cell structure and therefore it is easily consolidated with logic gates. In addition, since the MONOS method does not see the radical shortening of charge retention time caused by defects of an Si oxide film, hot-hole erasure which is likely to cause damage to an Si oxide film can be adopted, thus erasing time can be shortened by leaps and bounds, and resultantly the MONOS method gathers attention in recent years. Here, hot-hole erasure is described later in detail but briefly it is the method for erasing hot electrons stored in an Si insulator film as recorded information by inducing hot holes in a memory cell and neutralizing and erasing the electrons as the stored information.
As a split gate structure particularly suitable for miniaturization, there is a structure wherein a memory MOS transistor is formed with a sidewall by utilizing self-alignment (hereunder referred to as “self-aligned split gate structure”), (for example, refer to Patent documents 1 to 3).
In the case of a MONOS memory adopting such a self-aligned split gate structure, the gate length of a memory MOS transistor can be smaller than the minimum resolution size of lithography and therefore it has the advantages that operation current can be increased (operation frequency increases) and the area of a memory cell can largely be fractionized. The structure and operation of a conventional MONOS memory cell are hereunder explained briefly on the basis of FIG. 15.
Such a nonvolatile memory is composed of two MOS transistors; a memory MOS transistor Q1 that composes a storage node and a select MOS transistor Q2 that selects the storage node and retrieves information. The diffusion layer (source region) 406a of the select MOS transistor Q2 is connected to a common source line and a select gate electrode 403 is connected to a word line. Meanwhile, the diffusion layer (drain region) 406b of the memory MOS transistor Q1 is connected to a bit line and a memory gate electrode 405 is connected to a memory gate line.
The gate insulator film 404 of the memory MOS transistor Q1 is composed of a film of a three-layered structure; for example, from the surface of an Si substrate 401 in order, an Si oxide film (the first-layered film) 404a, an Si nitride film (the second-layered film) 404b and another Si oxide film (the third-layered film) 404c. 
With regard to the thickness of the gate insulator film, each of the first-layered film 404a, second-layered film 404b and third-layered film 404c is about 5 to 15 nm.
The gate insulator film 404 of the memory MOS transistor Q1 is formed after the gate electrode 403 of the select MOS transistor Q2 is formed and therefore it is formed also on the sidewall of the select gate electrode 403.
The thermal oxidation method is used for the formation of the first-layered Si oxide film 404a. The low-pressure thermal CVD method which is excellent in step coverage is used for the formation of the second-layered Si nitride film 404b, and the method of using dichlorosilane (SiH2Cl2) and ammonia (NH3) as the material gas is generally employed. For the formation of the third-layered Si oxide film 404c, either of the thermal oxidation method and the low-pressure thermal CVD method is commonly used and, generally speaking, the thermal oxidation method is dominantly used.
Writing operation is carried out by: applying prescribed voltages to the diffusion layer (source region) 406a and gate electrode 403 of the select MOS transistor Q2 and thus activating the select MOS transistor Q2; and simultaneously applying prescribed voltages to the diffusion layer (drain region) 406b and gate electrode 405 of the memory MOS transistor Q1. For example, the voltages of 0 V, 1 to 2 V, 3 to 5 V and a high voltage of 8 to 10 V are applied to the source region 406a, the gate electrode 403 of the select MOS transistor Q2, the drain region 406b and the gate electrode 405 of the memory MOS transistor Q1, respectively.
Under such voltage conditions, a high electric field is imposed on the boundary region between the select MOS transistor Q2 and the memory MOS transistor Q1, and resultantly hot electrons of large energy are generated in the Si substrate 401. Some of the hot electrons are injected to the side of the memory gate electrode 405 to which a high voltage is applied. At the time, most of the hot electrons are trapped in the Si nitride film 404b that constitutes a part of the gate insulator film of the memory MOS transistor Q1. Such an electron injection method is generally called the source side hot-electron injection method or the source side injection method.
Erasing operation is carried out by the method of: applying a negative bias to the memory gate electrode 405 of the memory MOS transistor Q1 and a positive bias to the diffusion layer 406b (drain region); generating hot holes by using band-to-band tunneling (BTBT); and injecting the hot holes into the Si nitride film 404b (hot-hole erasing). For example, erasing is carried out by applying 5 to 7 V to the drain region 406b, −9 to −11 V to the gate electrode 405 of the memory MOS transistor Q1, and 0 V or no voltage application to the source region 406a and the gate electrode 403 of the select MOS transistor Q2.
Retrieving operation is carried out by retrieving recorded information in compliance with whether a prescribed current is fed or not in accordance with the state of the threshold voltage of the memory MOS transistor Q1 when the select MOS transistor Q2 is activated.    [Patent document 1] JP-A No. 74389/1999    [Patent document 2] JP-A No. 46002/2003    [Patent document 3] JP-A No. 237540/2002
The problems of the MONOS memory of a split gate structure shown in FIG. 15 are explained on the basis of figures. FIGS. 16 and 17 are views obtained by enlarging the region A of FIG. 15.
As described above, the region where hot electrons are generated in the Si substrate 401 at the time of writing is located underneath the vicinity of the region where the select gate electrode 403 of the select MOS transistor Q2 and the memory gate electrode 405 of the memory MOS transistor Q1 are electrically separated. Some of the hot electrons generated from the position are injected toward the edge of the gate electrode 405 by the gate electric field of the memory MOS transistor Q1. Most of the injected hot electrons are trapped in the Si nitride film 404b having a large trapping sectional area and resultantly writing is carried out.
As shown in FIG. 16, in the event of the aforementioned writing, hot electrons are injected in the direction of the arrow while extending laterally and therefore some of the hot electrons are injected also into the sidewall region of the gate electrode 403 of the select MOS transistor Q2, in other words, the vertical region of the L-shaped Si nitride film 404b (the direction perpendicular to the Si substrate). Further, it is estimated that the distribution of the trapped electrons further expands by the influences of: the internal electric field in the Si nitride film 404b caused by the trapped electrons; and a high temperature environment of about 150° C.
Meanwhile, in the event of the injection of hot holes for erasing, hot holes are injected in the direction of the arrow from one end of the drain 406b of the memory MOS transistor Q1 as shown in FIG. 17. The hot holes generated in the high electric field region at the end of the drain 406b are injected into the Si nitride film 404b while being influenced by the electric field of the memory gate electrode 405 and slightly expanding toward the side of the select MOS transistor Q2.
The extension of the hot-hole injection in the lateral direction depends on injection conditions and is estimated to be 50 to 80 nm. As shown in FIG. 17, electrons existing in the region into which positive holes are injected are erased in microseconds, but the electrons existing outside the positive hole injected region has a very small positive hole density and therefore some electrons are unerased and remain. The amount of unerased electrons increases as the frequency of rewriting increases, and therefore the drawback here is that a prescribed threshold voltage cannot be secured even though erasing of electrons is carried out for the last time.
In order to avoid unerased electrons from remaining, it is necessary either to further shorten the gate length (Lmg) of the memory MOS transistor Q1 or to prolong the erasing time considerably. However, if Lmg is shortened, punch through occurs. For that reason, the lower limit of Lmg is about 60 nm.
In contrast, if the hot-hole injection time is prolonged, the following harmful effects appear: (1) the area of the charge pump power supply circuit for securing supply current increases, (2) the bottom gate oxide film 404a deteriorates and the charge retention time decreases, and (3) positive holes accumulate in the Si nitride film 404b in the vicinity of the drain 406b and the generation efficiency of hot holes lowers.